机译:准循环LDPC解码器的低复杂度存储器访问架构
Department or blectncal Engineer- ing, National Cheng Kung University, Tainan City, Taiwan, R.O.C;
Department or blectncal Engineer- ing, National Cheng Kung University, Tainan City, Taiwan, R.O.C;
Himax Technology, Tainan City, Taiwan, R.O.C;
Department or blectncal Engineer- ing, National Cheng Kung University, Tainan City, Taiwan, R.O.C;
error control coding; low-density parity-check (LDPC) codes; quasi-cyclic (QC) LDPC codes; partially parallel architecture; VLSI design;
机译:准循环LDPC解码器的低复杂度存储器访问架构
机译:准循环LDPC码的内存高效解码器架构
机译:准循环LDPC码的内存高效部分并行解码器架构
机译:基于高速,低存储器FPGA的基于LDPC解码器架构,用于准循环LDPC代码
机译:基于网格的准循环LDPC卷积码可实现节能解码器
机译:低复杂性解码下LDPC代码的错误指令
机译:准循环LDPC码的多层并行解码算法和VLSI架构
机译:LDpC码的存储器有效解码