System-MSPA Design of H.263 + Video Encoder/Decoder LSI for Videotelephony Applications

摘要

In this paper, a LSI design for video encoder and decoder for H.263+ video compression is presented. LSI operates under clock frequency of 27 MHz to compress QCIF (176×144 pixels) at the frame rate of 30 frame per second. The core size is 4.6?4.6 mm~2 in a 0.35 μm process. The architec- ture is based on bus connected heterogeneous dedicated mod- ules, named as System-MSPA architecture. It employs the fast and small-chip-area dedicated modules in lower level and controls them by employing the slow and flexible programmable device and an external DRAM.