Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs

摘要

In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In or- der to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM re- freshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under Several models which simulate each combination of them.