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Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit

机译:CMOS平方根电路的低动态功率和低泄漏功率技术

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A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (P_(at)) and leakage power (P_(st)), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The P_(at) of the new SR circuit at a clock frequency (f_c) of 490 MHz and a supply voltage (V_(dd)) of 0.75 V was 104.1μW, i.e., 21.6% that (482.3 μW) of a conventional SR circuit. The Pst of the new SR circuit was markedly reduced to 19.51 nW, which was only 1.69% that (1,153 nW) of the conventional SR circuit.
机译:开发了平方根(SR)算法,SR体系结构和泄漏电流减小电路,以降低动态功率(P_(at))和​​泄漏功率(P_(st)),同时保持CMOS SR电路的速度。使用这些技术,制造了90纳米CMOS LSI。在490 MHz的时钟频率(f_c)和0.75 V的电源电压(V_(dd))下,新SR电路的P_(at)为104.1μW,即是常规SR的(482.3μW)的21.6%电路。新SR电路的Pst显着降低至19.51 nW,仅是传统SR电路(1,153 nW)的1.69%。

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