In high level synthesis, Scheduling is an important stage which assigns each operation appeared in a data flow graph to a specific control step, of which results influence the design quality directly. This paper describes a scheduling approach for pipelined datapaths. Since few previous approaches estimate the inter connection cost between registers (register-to-register cost), our approach introduces a datapath model with the interconnection between registers across buses, and minimizes the total hardware cost including the register-to-register cost with the Force-Directed Scheduling.
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