An Occurrence Mechanism and Improving Method for the Output Waveform Distortion of CMOS Logic ICs

摘要

Waveform distortion at signal edge generally falls into two categories: hysteresis type and non hysteresis type. Non hysteresis type distortion has a flat portion in signal transition, but it will not give any serious problem except for timing oriented circuits. While, hysteresis type distortion which makes round trip between two threshold levels will affect logic judgment. Incorrect information will be transmitted if signal is seriously distorted.