Electrical Characterization of the Copper CMP Process and Derivation of Metal Layout Rules

摘要

Design rules were developed for the layout of copper Damascene interconnect layers to minimize the within-die resistance variation. The impact of various layout configurations on the metal sheet resistance was characterized using two different test vehicles. An increase in resistance was observed on wide lines and high pattern densities due to dishing and dielectric erosion, respectively. In addition to the above, narrow lines were severely impacted by the presence of wide adjacent features in close proximity. The pattern interaction distance for copper chemical-mechanical planarization (CMP) was calculated by analyzing the resistance variation at the edge of a density or width transition. In this work, the interaction distance was found to be on the order of 25μm (as opposed to a few millimeters for oxide CMP). From these results, a window of about 50 to 60μm was found to be necessary to obtain the effective pattern density for copper CMP. The resistance of the upper metal level was a strong function of the underlying layer density. Hence, multilevel pattern dependencies have to be considered when modeling and predicting the line resistance on a real design. However, unlike oxide polish, pattern density alone is insufficient to predict the final copper thickness. Width-dependent spacing rules are necessary to prevent clustering of features (narrow lines very close to wide buses) and avoid regions of very low density.