Gettering in high resistive float zone silicon wafers for silicon detector applications

摘要

An intrinsic gettering technique for float-zone highly resistive silicon using TCA+O/sub 2/ has been described. The capacitance-voltage technique was used to determine the flat-band voltage and stretch-out of MOS (metal oxide semiconductor) structures made on various oxides. It has found that this intrinsic getting process improves minority-carrier-generation lifetime and SiO/sub 2//Si interface properties, leading to the reduction of leakage current in the p-i-n detector configuration. Direct comparisons of intrinsic gettering and extrinsic gettering using As ion-implantation have been made. Intrinsic gettering has been found to be the dominant process.