A 0.5-to-3.5-GHz Full-Duplex Mixer-First Receiver With Cartesian Synthesized Self-Interference Suppression Interface in 65-nm CMOS

摘要

This article presents a wideband self-interference (SI) canceling full-duplex (FD) receiver. In-band linearity requirement for an FD receiver is studied. It is shown that an FD receiver requires a minimum IB-IIP3 which if not provided, results in sensitivity degradation. To provide the required out-of-band linearity, an eight-phase passive mixer-first architecture is chosen for the receiver. In order to achieve SI cancellation, quadrature components from TX replica are created, their magnitudes are scaled, and the approximated SI is injected to the receiver. The cancellation occurs after downconversion, in an RF to baseband (BB) cancellation domain. As a proof of concept, a prototype is fabricated and measured in a 65-nm CMOS process. More than 35-dB cancellation is measured for 10-MHz bandwidth (BW) 64-QAM modulated signals in a single RF downconverted domain. The noise figure (NF) in half-duplex (HD) and FD mode is 3.3 and 5.3 dB, respectively, with only 2-dB degradation for switching from HD to FD. The receiver has adjustable 30-to-50-dB conversion gain, consumes 20-58-mW power, and achieves IB-IIP3 of +6 dBm. The cancellation path achieves more than 35-dBm IIP3.