Parity Bit Signature in Response Data Compaction and Built-In Self-Testing of VLSI Circuits With Nonexhaustive Test Sets

摘要

The design of efficient time compression support hardware for built-in self-testing (BIST) is of great importance in the design and manufacture of VLSI circuits. The test data outputs in BIST are ultimately compressed by the time compaction hardware, commonly called a response analyzer, into signatures. Several output response compaction techniques to aid in the synthesis of such support circuits already exist in literature, and parity bit signature coupled with exhaustive testing is already well known to have certain very desirable properties in this context. This paper reports new time compaction techniques utilizing the concept of parity bit signature that facilitates implementing such support circuits using nonexhaustive or compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information as best as possible. Recently, Jone and Das proposed a multiple-output parity bit signature generation method extending the basic idea of Akers, for exhaustive testing of digital combinational circuits, where, given a multiple-output circuit, a parity bit signature is generated by first XORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. The method, as shown by the authors, preserves all the desirable properties of the conventional single-output response analyzers and can also be easily implemented by using the current VLSI technology. The subject paper further augments the aforesaid concepts of Jone and Das, and proposes a multiple-output parity bit signature for nonexhaustive testing of VLSI circuits. Design algorithms are proposed in the paper, and the simplicity and ease of their implementations are demonstrated with examples. Extensive simulation experiments on ISCAS 85 combinational benchmark circuits using FSIM, ATALANTA, and COMPACTEST programs demonstrate that the proposed signature generation method achieves high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. A performance comparison of the designed time compactors with conventional space-time compaction is also presented to demonstrate improved tradeoff for the new circuits in terms of fault coverage and the CUT resources consumed contrasted with existing designs, and to appreciate the resulting performance enhancements.