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Statistical modeling for postcycling data retention of split-gate flash memories

机译:统计模型,用于分离门闪存的后循环数据保留

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In developing an accurate lifetime-prediction model for postcycling data-retention failure rate of split-gate Flash memories, a floating-gate potential extraction method from the measured bit-cell-current data is proposed. Stress-induced leakage current through the coupling oxide caused by the source-side channel hot electron injection during program operation is the major cause for postcycling data-retention failure bits. Considering charge conservation and trap-assist-tunneling leakage current, the charge-gain behavior under low-temperature bake is modeled and the failure rate under various measured conditions can be predicted precisely. We have found that data-retention lifetime decreases as program/erase (P/E) cycling increases, while failing bits increase with numbers of P/E cycling.
机译:在建立用于分离栅闪存的数据保持失败率的循环寿命的精确寿命预测模型时,提出了一种从测量的位单元电流数据中提取浮栅电位的方法。在编程操作期间,由源侧通道热电子注入引起的应力引起的通过耦合氧化物的泄漏电流是造成数据保持失败位后循环的主要原因。考虑到电荷守恒和陷阱辅助隧穿漏电流,对低温烘烤下的电荷增益行为进行建模,并可以精确预测各种测量条件下的失效率。我们发现,数据保留寿命随着编程/擦除(P / E)循环次数的增加而减少,而失败位数随P / E循环次数的增加而增加。

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