机译:单个事件瞬态(SET)缓解电路与免疫叶节点
Indian Inst Technol Kharagpur Subir Chowdhury Sch Qual & Reliabil Kharagpur 721302 W Bengal India|UR Rao Satellite Ctr Reliabil & Qual Assurance Elect & Opt Syst Grp Bengaluru 560017 India;
Indian Inst Technol Kharagpur Subir Chowdhury Sch Qual & Reliabil Kharagpur 721302 W Bengal India;
UR Rao Satellite Ctr Adv Chip Design Div Bengaluru 560017 India;
Materials reliability; Single event transients; Positive SET mitigation circuit; bidirectional SET mitigation circuit; multiple nodes SET tolerance; SET immune leaf nodes; RHBD flip-flop;
机译:发生单周期或多周期单事件瞬态的电路的SET锁存概率新分析模型
机译:用于单事件瞬态缓解的自投票双模块冗余电路
机译:基于标准单元的组合电路中的单一事件多次瞬态
机译:SEIFF:软错误免疫触发器,用于缓解10 nm FinFET中的单事件翻转和单事件瞬态
机译:用于混合信号延迟锁定环(DLL)和时钟电路的单事件瞬态建模和缓解技术。
机译:缓解SiGe-HBT电流模式逻辑电路中的单事件效应
机译:空间任务中数字逻辑电路集免疫力的缓解与预测评估