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机译:多层导电基板存在下高频VLSI互连阻抗提取的解析表达式
Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA;
Green's function methods; VLSI; electric impedance; integrated circuit interconnections; millimetre wave integrated circuits; multilayers; 2-D Green function; CPU time reduction; continuous dipole expansion; electromagnetic parameters; high-frequency VLSI interconnect; impedance extraction; modified discrete complex images approximation; multiconductor current loops; multilayer conductive substrate; mutual impedance; self-impedance; substrate effects; Green's function; VLSI interconnect; high frequency; impedance; magnetic dipole; parasitic extraction; substrate;
机译:对“存在多层导电基板时高频VLSI互连阻抗提取的解析表达式”的更正
机译:具有多个基板的3-D IC中的水平互连和电感器的快速高频阻抗提取
机译:多层硅衬底上片上互连的串联阻抗参数的封闭式表达式
机译:VLSI的高频互阻抗提取在多层导电基板存在下互连
机译:考虑衬底效应的互连线的高频阻抗提取和用于未来VLSI互连线的单壁碳纳米管的探索。
机译:用于使用180GHz准光谐振器的电导率提取用于沉积在导电基板上的导电薄膜
机译:多层导电基板存在下高频VLsI互连阻抗提取的解析表达式