A Fast Analog Circuit Analysis Algorithm for Design Modification and Verification

摘要

This paper presents a fast analog circuit analysis algorithm, fundamental circuit-based circuit analysis, for circuits being repeatedly modified and verified in product development. The algorithm reuses previous circuit simulation result on successive changed circuit analysis to achieve simulation operation reduction. The algorithm is implemented with SPICE simulator on linear and nonlinear circuit applications with the proposed device delta models. The experiments show that the algorithm increases the speed of the circuit simulation five to ten times over directly simulations under the same simulation accuracy.