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Short-circuit energy dissipation modeling for submicrometer CMOS gates

机译:亚微米CMOS门的短路能量耗散建模

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A significant part of the energy dissipation in static complementary metal-oxide-semiconductor (CMOS) structures is due to short-circuit currents. In this paper, an accurate analytical model for the CMOS short-circuit energy dissipation is presented. First, the short-circuit energy dissipation of the CMOS inverter is modeled. The derived model is based on analytical expressions of the inverter output waveform which include the influences of both transistor currents and the gate-to-drain coupling capacitance. Also, the effect of the short-circuiting transistor's gate-source capacitance on the short-circuit energy dissipation, is taken into account. The /spl alpha/-power law MOS model that considers the carriers' velocity saturation effect of submicrometer devices is used. Second, the inverter model is extended to static CMOS gates by using reduction techniques of series- and parallel-connected transistors. The results produced by the suggested model for a commercial 0.8-/spl mu/m process, show very good agreement with SPICE simulations.
机译:静态互补金属氧化物半导体(CMOS)结构中大部分的能量耗散是由于短路电流引起的。本文提出了CMOS短路能量耗散的精确分析模型。首先,对CMOS反相器的短路能量耗散进行建模。推导的模型基于逆变器输出波形的解析表达式,其中包括晶体管电流和栅极至漏极耦合电容的影响。同样,考虑了短路晶体管的栅极-源极电容对短路能量耗散的影响。使用/ spl alpha /-幂律MOS模型,该模型考虑了亚微米器件的载流子速度饱和效应。其次,通过使用串联和并联晶体管的缩减技术,将逆变器模型扩展到静态CMOS门。建议的模型用于商业0.8- / spl mu / m工艺的结果表明,与SPICE模拟非常吻合。

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