In this paper, buffer and NAND-NOR adiabatic gates are compared to a gate designed with the traditional complementary metal-oxide-semiconductor (CMOS) approach. The comparison is carried out assuming both an assigned power supply and by setting its value in such a way as to minimize power consumption. General relationships, which are independent of process parameters, as well as being simple enough to be used in a pencil-and-paper evaluation, are calculated. The analysis is developed id detail for the fully adiabatic gates and extended to include partially adiabatic circuits such as 2N-2P and 2N-2N2P. The analytical results are validated by SPICE simulations using 0.8-/spl mu/m CMOS technology. The analysis shows that with the technology considered and a fan-out of three, the adiabatic buffer is advantageous at power clock rise times higher than 3 ns and 23 ns for the nonoptimized and the optimized design, respectively, assuming a 100-fF load capacitance. These rise times increase to 22 ns and 384 ns for the NAND-NOR gate. Moreover, all the minimum rise times increase linearly when the fan-out of the gate is increased.
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机译：在本文中，将缓冲器和NAND-NOR绝热门与采用传统互补金属氧化物半导体（CMOS）方法设计的门进行了比较。假定既分配了电源又通过以最小化功耗的方式设置其值来进行比较。计算了独立于过程参数的通用关系，并且该通用关系足够简单，可以用在纸笔评估中。分析是针对完全绝热的门而开发的，并扩展到包括部分绝热的电路，例如2N-2P和2N-2N2P。使用0.8- / spl mu / m CMOS技术的SPICE仿真验证了分析结果。分析表明，考虑到技术，并且扇出为三，绝热缓冲器在功率时钟上升时间分别大于3 ns和23 ns的情况下，对于非优化和优化设计而言都是有利的，假设负载电容为100fF 。对于NAND-NOR门，这些上升时间增加到22 ns和384 ns。此外，当门的扇出量增加时，所有最小上升时间都会线性增加。
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