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机译:具有65nm CMOS技术的0.36 pJ /位,0.025 mm2、12.5 Gb / s的前向时钟接收器,具有无卡滞延迟锁定环路和半位延迟线
Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Inter-University Semiconductor Research Center (ISRC), Seoul, Seoul, South KoreaSouth Korea;
Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Inter-University Semiconductor Research Center (ISRC), Seoul, Seoul, South KoreaSouth Korea;
Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Inter-University Semiconductor Research Center (ISRC), Seoul, Seoul, South KoreaSouth Korea;
Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Inter-University Semiconductor Research Center (ISRC), Seoul, Seoul, South KoreaSouth Korea;
AnaPass, Seoul, South Korea;
Department of Electrical and Computer Engineering, College of Engineering, Seoul National University, Inter-University Semiconductor Research Center (ISRC), Seoul, Seoul, South KoreaSouth Korea;
Jitter; Receivers; Timing; Clocks; Bandwidth; Detectors; Transceivers;
机译:10 Gb / s 0.71 pJ / bit转发时钟接收器,可承受65 nm CMOS中的高频抖动
机译:在65nm CMOS中使用基于电阻反馈反相器的驱动器的1pJ / bit,10Gb / s / ch前向时钟发送器
机译:65 nm CMOS的9.6 Gb / s 1.22 mW / Gb / s数据抖动混合转发时钟接收器
机译:具有采样交换方案和半位延迟线的0.36 pJ /位,12.5 Gb / s转发时钟接收器
机译:用于低功耗互连的40-NM CMOS中的52 GB / S子1-PJ /位PAM4接收器