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首页> 外文期刊>IEEE transactions on biomedical circuits and systems >An Improved Update Rate CDR for Interference Robust Broadband Human Body Communication Receiver
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An Improved Update Rate CDR for Interference Robust Broadband Human Body Communication Receiver

机译:一种用于干扰鲁棒宽带人体通信接收机的改进更新速率CDR

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摘要

Broadband Human Body Communication (HBC) enables energy efficient communication between body area network devices by utilizing the electrical conductivity property of the human body. However, environmental interference remains a primary bottleneck in its implementation. An integrating front-end receiver with resettable integration followed by periodic sampling can be utilized to enable interference robust broadband HBC. However, as required in all broadband communication systems, a Clock Data Recovery (CDR) loop is necessary to correctly sample the received data at the appropriate instant. The CDR is required to be sensitive to the clock-data phase mismatch at the receiver end and take corrective action for reducing it, similar to the CDR of a traditional receiver. In addition to that, the CDR for a broadband HBC receiver also requires to be tolerant to environmental interference. This paper analyzes the traditional Baud Rate CDR for an integrating front-end receiver and proposes a modified integrating CDR architecture with a higher update rate. Simulation results show 2.5X higher clock data frequency offset tolerance of the proposed CDR compared to the traditional Baud Rate CDR, > 1.25X higher clock data frequency offset tolerance in presence of interference and > 10 interference frequency offset tolerance with respect to the integration clock. The proposed CDR is also implemented in a Xilinx Spartan-3E FPGA board to validate its closed loop functionality in real time.
机译:宽带人体通信(HBC)通过利用人体的电导率特性实现人体区域网络设备之间的节能通信。但是,环境干扰仍然是其实施的主要瓶颈。具有可重置集成并随后进行周期性采样的集成前端接收机可用于实现抗干扰能力强的宽带HBC。但是,按照所有宽带通信系统的要求,时钟数据恢复(CDR)环路对于在适当的时刻正确采样接收到的数据是必需的。与传统接收器的CDR相似,要求CDR对接收器端的时钟数据相位失配敏感,并采取纠正措施以减少它。除此之外,宽带HBC接收器的CDR还需要容忍环境干扰。本文分析了集成前端接收器的传统波特率CDR,并提出了一种具有更高更新速率的改进的集成CDR体系结构。仿真结果表明,与传统的波特率CDR相比,拟议CDR的时钟数据频率偏移容忍度高2.5倍,在存在干扰的情况下,时钟数据频率偏移容忍度高1.25倍,而集成时钟的干扰频率偏移容忍度则高10倍。提议的CDR还可以在Xilinx Spartan-3E FPGA板上实现,以实时验证其闭环功能。

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