A parallel unification machine

摘要

A parallel unification machine (PUM) that speeds up the unification algorithm is proposed. The PUM partitions unification into a match step and a consistency-check step, conducts these two steps concurrently, and takes advantage of the match parallelism. The machine architecture, algorithms, data formats, and processor organization are described. The machine has been simulated at the register-transfer level with the ISPS computer description language. The simulated performance is compared with that of two serial unification coprocessors. Significant speedup is observed.