Fine-Grained Scheduling in Heterogeneous-ISA Architectures

摘要

Given the ever increasing demand for improved computational capabilities, heterogeneous-ISA multi-core architectures have emerged as a promising alternative to improve single-threaded performance. Such architectures comprise of multiple cores that differ not just in micro-architectural parameters but also in their Instruction Set Architectures (ISAs). Programs have affinity towards different ISAs during its execution based on nature of code and data input. To extract maximum performance gain, we need to ensure that at every point in the program's execution, the program runs on its best affine core with minimum migration overhead. In this letter, we propose a function-wise fine grained scheduling algorithm which schedules every function of a program to its most affined ISA. Results show that our function-based scheduler can achieve speedup of up to 22.9 percent over state-of-the-art in heterogeneous-ISA architectures.