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Design and analysis of a large-scale multicast output buffered ATM switch

机译:大型组播输出缓冲ATM交换机的设计与分析

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Proposes and analyzes a recursive modular architecture for implementing a large-scale multicast output buffered ATM switch (MOBAS). A multicast knockout principle, an extension of the generalized knockout principle, is applied in constructing the MOBAS in order to reduce the hardware complexity (e.g., the number of switch elements and interconnection wires) by almost one order of magnitude. In the proposed switch architecture, four major functions of designing a multicast switch: cell replication, cell routing, cell contention resolution, and cell addressing, are all performed distributively so that a large switch size is achievable. The architecture of the MOBAS has a regular and uniform structure and, thus, has the advantages of: (1) easy expansion due to the modular structure, (2) high integration density for VLSI implementation, (3) relaxed synchronization for data and clock signals, and (4) building the center switch fabric (i.e., the multicast grouping network) with a single type of chip. A two-stage structure of the multicast output buffered ATM switch (MOBAS) is described. The performance of the switch fabric in cell loss probability is analyzed, and the numerical results are shown. The authors show that a switch designed to meet the performance requirement for unicast calls will also satisfy multicast calls' performance. A 16/spl times/16 ATM crosspoint switch chip based on the proposed architecture has been implemented using CMOS 2-/spl mu/m technology and tested to operate correctly.
机译:提出并分析了用于实现大规模多播输出缓冲ATM交换机(MOBAS)的递归模块化体系结构。多播敲除原理是通用敲除原理的扩展,被应用于构造MOBAS,以便将硬件复杂性(例如,开关元件和互连线的数量)降低近一个数量级。在提出的交换机体系结构中,设计多播交换机的四个主要功能:信元复制,信元路由,信元竞争解决和信元寻址都可以分布式执行,因此可以实现较大的交换机大小。 MOBAS的结构具有规则且统一的结构,因此具有以下优点:(1)由于采用模块化结构,易于扩展;(2)用于VLSI实施的集成密度高;(3)数据和时钟的轻松同步信号;以及(4)用单一类型的芯片构建中央交换结构(即,组播分组网络)。描述了组播输出缓冲ATM交换机(MOBAS)的两阶段结构。分析了交换结构在信元丢失概率上的性能,并给出了数值结果。作者表明,为满足单播呼叫的性能要求而设计的交换机也将满足组播呼叫的性能。基于所建议架构的16 / spl times / 16 ATM交叉点交换芯片已使用CMOS 2- / spl mu / m技术实现,并经过测试可正常运行。

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