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Communication and migration energy aware task mapping for reliable multiprocessor systems

机译:用于可靠的多处理器系统的通信和迁移能量感知任务映射

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Heterogeneous multiprocessor systems-on-chip (MPSoCs) are emerging as a promising solution in deep sub-micron technology nodes to satisfy design performance and power requirements. However, shrinking transistor geometry and aggressive voltage scaling are negatively impacting the dependability of these MPSoCs by increasing the chances of failures. This paper proposes an offline (design-time) task remapping technique to minimize the communication energy and task migration overhead of an application mapped on a heterogeneous multiprocessor system for all processor fault-scenarios. The proposed technique involves two steps- (1) Communication Energy driven Design Space Exploration (CDSE) to select an initial mapping and (2) Communication energy and Migration overhead aware Task Mapping (CMTM) for different fault-scenarios. The CDSE is formulated as a Mixed Integer Quadratic Programming (MIQP) problem and solved using an energy-gradient based heuristic. The CMTM problem is solved using a fast heuristic with the starting mapping selected using CDSE step. The proposed two steps technique is compared with state-of-the-art approaches through rigorous simulations with synthetic and real application graphs. Results demonstrate that the proposed CDSE reduces design space exploration time by 99% with a maximum variation of 5% from the optimal solution obtained by solving the MIQP problem directly. Further, the proposed CMTM reduces communication energy by an average 35% and migration overhead by an average 20% for all single and double fault-scenarios as compared to the existing fault-tolerant techniques. The CMTM also achieves over 30x reductions in execution time for large problem sizes with a maximum deviation of 15% from the minimum communication energy achievable with the given application on a given architecture. For streaming multimedia applications, the proposed technique delivers 50% higher throughput per unit energy as compared to the existing approaches.
机译:异构多处理器片上系统(MPSoC)逐渐成为一种有前途的解决方案,可满足深亚微米技术节点的需求,以满足设计性能和功耗要求。但是,缩小的晶体管几何形状和激进的电压缩放比例会通过增加出现故障的机会而对这些MPSoC的可靠性产生负面影响。本文提出了一种离线(设计时)任务重映射技术,以针对所有处理器故障情况,将映射在异构多处理器系统上的应用程序的通信能量和任务迁移开销降至最低。所提出的技术涉及两个步骤-(1)通信能量驱动的设计空间探索(CDSE)以选择初始映射,以及(2)针对不同故障情况的通信能量和迁移开销感知任务映射(CMTM)。 CDSE被公式化为混合整数二次规划(MIQP)问题,并使用基于能量梯度的启发式方法进行求解。通过使用CDSE步骤选择的起始映射的快速启发式方法解决了CMTM问题。通过使用合成图和实际应用图进行严格的模拟,将建议的两步技术与最新技术进行了比较。结果表明,与直接解决MIQP问题获得的最佳解决方案相比,拟议的CDSE将设计空间探索时间减少了99%,最大变化幅度为5%。此外,与现有的容错技术相比,对于所有单一和双重故障情形,建议的CMTM可以平均减少35%的通信能量,并平均减少20%的迁移开销。对于大型问题,CMTM还可以将执行时间减少30倍以上,与给定体系结构上给定应用程序所能达到的最小通信能量之间的最大偏差为15%。对于流媒体多媒体应用,与现有方法相比,所提出的技术可将每单位能量的吞吐量提高50%。

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