Scan-Based Diagnostics Assists Yield

摘要

As technologies move below 130 nm, the IC industry has seen a significant change in the type of defects encountered. Feature-related defects are becoming more prevalent than particle-driven defects in nanometer designs. Due to lithography hardware constraints and shrinking design geometries, resolution enhancement techniques such as optical and process correction are necessary but increase the difficulties associated with production ramp and yield learning. Improving yield in the nanometer domain requires solutions from design through manufacturing. Design for manufacturing (DFM) is one of the important methods to help enhance yield. Traditional in-line inspection techniques often cannot detect defects due to DFM marginalities that can lead to yield loss. Additionally, fabless companies may not have access to in-line data for driving yield learning. As a result, yield engineers must rely on information gained from parametric test and wafer sort to achieve yield goals.