IC manufacturers continue to aggressively pursue design rule shrinks, driven by the benefits of reduced die cost and increased IC functionality. Lithography is the main driver of shrink, with current feature resolutions now reaching below 40nm half pitch. Overlay requirements continue to tighten, however, scaling at least linearly along with resolution. Increased IMA beyond ～1.35 using high-index fluids and glass is feasible, but is challenged by the need to mature new optical materials and immersion fluids, as well as by limited extendibility and the expected late availability of applications for leading device manufacturers. During the 2008-09 timeframe, extending ArF lithography with double-patterning techniques to reduce k1 below 0.25 is expected to be the only technology available for volume manufacturing at sub-40nm resolution. Double-patterning is relatively straightforward to apply to the highly repetitive patterns of NAND flash devices, but is more difficult for the complex patterns encountered with DRAM and logic devices, where the tighter tolerances for overlay and CD may affect the scaling efficiency. In the long term, wavelength reduction with EUV is the preferred technology for volume manufacturing of devices beyond 32nm. Though not yet ready for volume production, EUV appears likely to offer significant cost and cycle-time advantages over the interim technology of double-patterning. That potential is driving broad collaboration to mature the light source, mask and resist infrastructure for this promising next-generation optical lithography technology.
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