A fine grain mapping strategy for multiprocessor systems especially suitable for RISC and VLIW type MIMD computers is described. The objective of the strategy is to minimise the total execution time of the application algorithms that are to be executed on the target systems. An application algorithm which has been coded as a straight line program is compiled to generate intermediate codes. This code is then represented by a data dependence graph. A node in the graph corresponds to the operation of one intermediate code statement, and arcs between nodes represent the data dependence between operations. The mapping strategy, called SR-mapper, is a generalised list scheduler. When SR-mapper does the mapping procedure, the data dependence between nodes, the pipeline effect of each processing element within the system, and the communication cost between processing elements are considered. SR-mapper uses slot reservation technique to insert send nodes for the immediate successor nodes when a node has been scheduled to maintain the data dependence between nodes and to achieve the synchronisation between processing elements. SR-mapper has been implemented and several scientific application algorithms, such as matrix multiplication, L-U decomposition, weighted median filter, convolution kernel etc. have been used as the testing inputs.
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