FPGR platforms mode designing foster end cheaper

摘要

Remember those days when electronic engineers, called hardware designers, de-signed those chips called ASICs and ASSPs? They had to pay millions of dollars to buy EDA tools and then spend 18 months and even years designing those chips for a few or even just one product in an application space. To make matters worse, if the specifications of the design changed or if a flaw was found late in the design cycle, the design team had spend millions of dollars to respin masks or even completely redesign the chip. That was hell.. .that is until they found out they could really replace the chip along with a few others on the printed-circuit board with a single FPGA.