New domino logic precharged by clock and data

摘要

A clock-and-data precharged dynamic (CDPD) circuit technique in CMOS is presented. It gives a fast one-clock-cycle decision to multilevel logic and has small clock loads, low peak current, small area and low power-delay product. The technique is highly flexible in logic design. For the given example, a 324 bit binary-lookahead-carry chain, the speed improvement can be as high as 40-50% compared to the static circuit and 30% to the normal domino circuit arrangements while the area is reduced by 15-30%.