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Low power fully differential frequency doubler

机译:低功耗全差分倍频器

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A novel fully differential frequency doubler is proposed based on CMOS technology, where a stacked push-push configuration is used to generate differential output. Compared to previously reported doublers, the proposed topology has advantages in power dissipation, fundamental frequency rejection, and simplicity. By utilising the proposed doubler, a low power direct-conversion up-mixer is designed for 900 MHz applications. The fabricated up-mixer shows 5.5 dB of power conversion gain and 7.5 dBm of output IP3, while dissipating total current of 4.5 mA from 1.25 V supply. [References: 4]
机译:提出了一种基于CMOS技术的新型全差分倍频器,其中采用堆叠推挽式配置来产生差分输出。与以前报道的倍频器相比,该拓扑在功耗,基频抑制和简单性方面具有优势。通过利用建议的倍频器,为900 MHz应用设计了一种低功率直接转换上混器。制成的上混频器显示出5.5 dB的功率转换增益和7.5 dBm的输出IP3,同时从1.25 V电源消耗4.5 mA的总电流。 [参考:4]

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