Architecture of transform circuit for video decoder supporting multiple standards

摘要

Presented is an area-efficient architecture of a VLSI circuit that can perform various DCT-based transforms for a video decoder supporting multiple standards such as JPEG, MPEG-4, VC-1 and H.264. The proposed architecture uses a novel concept of a delta coefficient matrix and shares resources such as adders and shifters as much as possible. Multipliers are not included.