Dither-based calibration of bit weights in pipelined-SAR ADCs with fast convergence speed using partially split structure

摘要

A background calibration technique is proposed to correct bit weights in pipelined-successive-approximation-register (SAR) analogue-to-digital converters (ADCs). By splitting the second stage, the input signal interference is mostly removed, thereby greatly enhancing the convergence speed of the algorithm. Besides, the dither signal assists to eliminate mismatch issues between the partially split ADCs, thus relaxing the analogue overheads. According to the simulation, after calibration, the spurious-free-dynamic-range and signal-to-noise-and-distortion-ratio are improved from 53.2 to 88.2 dB and 49.5 to 75.2 dB, respectively. The calibration algorithm converges with about only 600 K samples.