23 × 12 μm three-stage amplifier using sub-threshold active cascode compensation capable of driving very-large-load with no-upper-limit

摘要

An ultra-area-efficient three-stage amplifier is proposed by using sub-threshold active cascade compensation, which is able to drive very-large or ultra-large capacitive loads without sacrificing stability and power. Besides, external feed-forward path and slew-rate enhancer can significantly improve the large-signal transient response of the circuit. Designed and verified in 28 nm CMOS technology, the proposed amplifier occupies die area of 0.00028 mm(2) and consumes a power of 16.5 mu W from 1.05 V supply. In addition, it can provide over 85 dB DC gain and is stable for any load larger than 4 nF, while the size of the entailed compensation capacitance is only 40 fF.