SoC technical difficulties ahead; stand by

摘要

Despite the assurances of foundries, ASIC vendors and tool suppliers that the problems with 130-nanometer CMOS are well in hand and that 90 nm is ready to use, there is arumbling of voices from experienced design teams that not all is well. Teams that have actually executed 150-nm and 130-nm designs say that there are in fact profound areas of concern with the technology. Some of those are static-problems that give you a "take it or leave it" choice. Some are much harder to pin down-problems that come and go, that may have been learning curve issues at a particular foundry or that require significant adjustment to the design flow but are not showstoppers.