Compact Physical IR-Drop Models for Chip/Package Co-Design of Gigascale Integration (GSI)

摘要

The supply voltage decrease and power density increase of future GSI chips demand accurate models for the IR-drop. Compact physical IR-drop models of on-chip power/ground distribution networks are derived for two generic types of packages. In the early stages of design, these models enable accurate estimates of all required power/ground grid interconnect dimensions and chip pad counts that are needed for power distribution. The models also quantify the tradeoff between on-chip interconnect dimensions and the number of I/O pads required for power distribution and therefore enable rigorous chip/package co-design. Comparison with SPICE simulations show less than 1% and 5% error for the wire-bond package and the flip-chip package, respectively.