Enhanced Drain Current of 4H-SiC MOSFETs by Adopting a Three-Dimensional Gate Structure

摘要

4H-SiC (0001) metal–oxide–semiconductor field-effect transistors (MOSFETs) with a 3-D gate structure, which has a top channel on the (0001) face and side-wall channels on the ${hbox{11}bar{hbox{2}}hbox{0}}$ face, have been fabricated. The 3-D gate structures with a 1–5-$muhbox{m}$ width and a 0.8- $muhbox{m}$ height have been formed by reactive ion etching, and the gate oxide has been deposited by plasma-enhanced chemical vapor deposition and then annealed in $hbox{N}_{2}hbox{O}$ ambient at 1300 $^{circ}hbox{C}$. The fabricated MOSFETs have exhibited good characteristics: The $I_{rm ON}/I_{rm OFF}$ ratio, the subthreshold swing, and $V_{rm TH}$ are $hbox{10}^{9}$, 210 mV/decade, and 3.5 V, respectively. The drain current normalized by the gate width is increasing with decreasing the gate width. The normalized drain current of a 1-$muhbox{m}$-wide MOSFET is 16 times higher than that of a conventional planar MOSFET.