Investigation of Key Technologies for Poly-Si/TaN/HfLaON/IL ${rm SiO}_{2}$ Gate-Stacks in Advanced Device Applications

摘要

We demonstrated for the first time integration of a poly-Si/TaN/HfLaON/IL ${rm SiO}_{2}$ gate-stacks into high-performance sub-30-nm nMOSFETs using a gate-first process flow successfully. The properties of TaN/HfLaON/IL ${rm SiO}_{2}$ gate-stacks were studied. The results showed that the HfLaON gate dielectric material exhibited excellent thermal stability and electrical characteristics. A three-step dry etching method used to etch poly-Si/TaN/HfLaON/IL ${rm SiO}_{2}$ gate-stack was proposed to provide an effective pathway for patterning the complex gate-stacks. At $V_{rm DS}=V_{rm GS}=0.9~{rm V}$, the drive current $I_{rm ON}$ of 410 $mu{rm A}/mu{rm m}$ was achieved at an OFF-state leakage current $I_{rm OFF}$ of 180 ${rm nA}/mu{rm m}$. The threshold voltage of saturation extracted at $I_{rm DS}$ of 3 $mu{rm A}/mu{rm m}$ was 0.14 V. The subthreshold slope of 92 mV/decade and drain induced barrier lowering of 93 mV/V were obtained.