Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice

摘要

Silicon-lattice distortion in the 50-$mu{rm m}$-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn $mu$-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si $[004]$ plane showed a maximum tilt value of ${+}{rm 0.45}^{circ}$ and ${-}{rm 0.25}^{circ}$, respectively, over the $mu$ -bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ${sim}{rm 1000}~{rm MPa}$ of tensile stress and ${sim}{-}{rm 200}~{rm MPa}$ of compressive stress, respectively, over the $mu$-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.