机译:考虑电源电压和关断电流的III-V和Si nMOSFET(门长度= 13 nm)的综合性能基准
Components Res., Intel Corp., Hillsboro, OR, USA;
III-V semiconductors; MOSFET; capacitance; elemental semiconductors; gallium arsenide; indium compounds; nanowires; semiconductor device models; semiconductor doping; silicon; GaAs; III-V nMOSFETs; InAs; OFF-current; Si; atomistic full-band ballistic quantum transport simulation; capacitance; gate length; parasitic resistance; silicon nanowire nMOSFETs; size 13 nm; source-drain doping; supply voltage; switching delay; Capacitance; Logic gates; MOSFET; Performance evaluation; Silicon; III-V semiconductor materials; MOSFET; nanoscale devices; nanowires (NWs); semiconductor device modeling; semiconductor device modeling.;
机译:在半微米BiCMOS栅极的速度和NMOSFET可靠性之间进行电源电压设计折衷
机译:阈值电压灵敏度为0.1 / spl mu / m沟道长度,具有背栅偏置的全耗尽SOI NMOSFET
机译:使用虚拟源注入速度模型,将高性能逻辑晶体管DC基准化为III-V和Si三栅极n-MOSFET之间的7 nm技术节点
机译:掺杂剂型材的综合设计方法,以抑制20nm NMOSFET中的栅极引起的阈值电压变异性
机译:超越Si-CMOS缩放限制的用于VLSI的高性能III-V nMOSFET的设计,制造和表征。
机译:fT高于460-GHz的50nm以下50nm nMOSFET的小信号性能和建模
机译:具有高移动通道的15nm栅极长度双栅极N-MOSFET的性能评估:III-V,GE和SI