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首页> 外文期刊>Electron Devices, IEEE Transactions on >High-Voltage Electron Injection Enhanced TC-LIGBT on 1.5- μm -Thin SOI Layer for Reducing the Forward Voltage Drop
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High-Voltage Electron Injection Enhanced TC-LIGBT on 1.5- μm -Thin SOI Layer for Reducing the Forward Voltage Drop

机译:1.5μm的薄层土壤上的高压电子注入增强型TC-LIGHT可减少正向压降

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摘要

In this paper, a new high-voltage electron injection enhanced tridimensional channel lateral insulated gate bipolar transistor (EIETC-LIGBT) on 1.5- μm -thin silicon-on-insulator (SOI) layer is proposed to reduce the forward voltage drop. Based on the previous TC-LIGBT we have proposed, an extra floating p-layer is added at the emitter side of the proposed EIETC-LIGBT. The region locating between the separated p-body cells and the floating p-layer is the high doped n-type electron injection efficiency modulation (EIEM) region. Above the EIEM region, several virtual polygate structures connected to the emitter are fabricated between the separated p-body cells and the floating p-layer. The highly doped EIEM region can help the proposed structure to reduce the forward voltage drop by increasing the electron injection efficiency. The virtual gate structures are contributed to the forward-biased safe operating area of the proposed structure. By optimizing the doping of the EIEM region and the width of the virtual gate structures, an EIETC-LIGBT with the forward voltage drop of 3.4 V at VGE=10 V and JCE=100 A/cm 2 can be achieved, which has an improvement of 17% compared with the previous TC-LIGBT structure on the same thin SOI layer without sacrificing the current capability.
机译:本文提出了一种在1.5μm的薄绝缘体上硅(SOI)层上的新型高压电子注入增强型三维沟道横向绝缘栅双极型晶体管(EIETC-LIGBT),以减小正向压降。基于我们之前提出的TC-LIGBT,在提出的EIETC-LIGBT的发射极增加了一个额外的浮置p层。位于分离的p体单元与浮置p层之间的区域是高掺杂n型电子注入效率调制(EIEM)区域。在EIEM区域上方,在分离的p体单元与浮置p层之间制造了几个连接到发射极的虚拟多栅极结构。高掺杂的EIEM区域可通过提高电子注入效率来帮助所提出的结构减少正向电压降。虚拟门结构有助于该结构的前向安全操作区域。通过优化EIEM区域的掺杂和虚拟栅极结构的宽度,可以实现在VGE = 10 V和JCE = 100 A / cm 2时具有3.4 V正向压降的EIETC-LIGBT,具有改进在相同的薄SOI层上,与先前的TC-LIGBT结构相比,它的电流损耗仅为17%,而不会牺牲电流性能。

著录项

  • 来源
    《Electron Devices, IEEE Transactions on》 |2016年第12期|4873-4879|共7页
  • 作者单位

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

    National ASIC System Engineering Research Center, Southeast University, Nanjing, China;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Insulated gate bipolar transistors; Silicon-on-insulator; Doping; High-voltage techniques;

    机译:绝缘栅双极型晶体管;绝缘体上硅;掺杂;高压技术;

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