New Strained LDMOS With Ultralow ON-Resistance by Si1−yCy Source Stressor for About 20 V Low-Voltage Applications

摘要

A novel low ON-resistance strained lateral double-diffused MOSFET (LDMOS) with silicon-carbon (Si_1−yC_y) source is proposed for low-voltage applications. Due to the lattice mismatch between silicon and Si_1−yC_y, the source-side Si_1−yC_y stressor introduces the lateral tensile stress and vertical compressive stress along the conduction path to enhance the electron mobility in the channel and drift regions and hence improves the ON-state characteristics. As the stress relaxation in the drift region, the strain-induced breakdown voltage (BV) deterioration can be neglected. The simulation results show that the ON-resistance ( ${R}_{ext {on}}$ ) of the proposed device is decreased by 19.2% compared with the conventional LDMOS without strain at a gate overdrive voltage ( ${V}_{ext {GS}}$ – ${V}_{ext {T}}$ ) of 1 V. At the same time, the novel LDMOS achieves 47% and 28.8% increment in the drive current ( ${I}_{ext {D,sat}}$ ) and peak transconductance ( ${G}_{ext {m,peak}}$ ), respectively, while keeping a nearly identical BV of 23.08 V. Besides, the improved cutoff frequency ( ${f}_{ext {T}}$ ) and transconductance-to-current ratio ( ${G}_{ext {m}}/{I}_{ext {D}}$ ) are also obtained in the novel LDMOS.