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Quantum Transport Study of Si Ultrathin-Body Double-Gate pMOSFETs:${I}$${V}$,

机译:Si超薄双栅极pMOSFET的量子传输研究: $ {I} $ $ {V} $

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摘要

A comprehensive quantum transport study of ultrathin-body silicon double-gate pMOSFETs with gate length${L}_{extsf {g}}= extsf {14}$, 10, and 7 nm is performed by in-house developed nonequilibrium Green’s function solver employing the six-band${k} cdot {p}$Hamiltonian. The effects of channel length, body thickness, as well as confinement and transport crystal orientations are studied systematically. Both${I}$${V}$and${C}$${V}$characteristics are analyzed in this paper. Furthermore, the CMOS performance benchmarking results, such as switching delay, energy consumption, and their product, are calculated with the influence of parasitic resistances and capacitances treated in an appropriate way. It is found that the crystal orientation effect on drive current is significant at both long and short channel lengths, while its effect on effective capacitance is more observable at${L}_{extsf {g}} = extsf {7}$nm. The drive current at${L}_{extsf {g}} = extsf {14}$nm and${L}_{extsf {g}} = extsf {7}$nm can be well explained by average ballistic hole velocity and source-to-drain tunneling ratio, respectively. Meanwhile, the effective capacitance is not only determined by the density of states but also affected by the distribution of holes in the confined direction. Both intrinsic and extrinsic performance assessments suggest that (001)/[100] and (110)/[001] are the optimal confinement/transport crystal orientation configurations at${L}_{extsf {g}}= extsf {7}$nm, while${(}extsf {110}{)}/[overline {1}extsf {10}]$and${(}extsf {110})/[overline {1}extsf {11}]$are the best choices at longer gate lengths. As${L}_{extsf {g}}$shrinks, both intrinsic and extrinsic performances will be better at a scaled body thickness.
机译:具有栅极长度的超薄体硅双栅极pMOSFET的全面量子传输研究 n $ {L} _ { t​​extsf {g}} = textsf {14} $ n,10和7 nm被执行由内部开发的非平衡Green函数求解器采用六频带 n $ {k} cdot {p} $ nHamiltonian。系统研究了沟道长度,主体厚度以及限制和传输晶体取向的影响。两者 n <内联公式xmlns:xlink = “ http://www.w3.org/1999/xlink ”> $ {I} $ n– n $ {V} $ nand n $ {C} $ n– n $ {V} $ n特征。此外,在以适当方式处理的寄生电阻和电容的影响下,可以计算出CMOS性能基准测试结果,例如开关延迟,能耗及其乘积。发现在长和短沟道长度上,晶体取向对驱动电流的影响都很显着,而对有效电容的影响在 n $ {L} _ { t​​extsf {g}} = textsf {7} $ nnm。在 n $ {L} _ { textsf {g}} = textsf {14} $ nnm和 n $ {L} _ { t​​extsf {g}} = textsf {7} $ nnm可以分别由平均弹道速度和源漏隧穿比很好地解释。同时,有效电容不仅由状态密度决定,而且还受孔在有限方向上的分布的影响。内部和外部性能评估均建议(001)/ [100]和(110)/ [001]是在 n $ {L} _ { t​​extsf {g}} = textsf {7} $ nnm,而 n $ {(} textsf {110} {)} / [ overline {1} textsf {10}] $ nand n $ {(} textsf {110})/ [ overline { 1} textsf {11}] $ 在较长的浇口长度下没有最佳选择。为 n <内联公式xmlns:xlink = “ http://www.w3.org/1999/xlink ”> $ {L} _ { t​​extsf {g}} $ n收缩,按比例缩放的身体厚度,内在和外在性能都会更好。

著录项

  • 来源
    《Electron Devices, IEEE Transactions on》 |2019年第1期|655-663|共9页
  • 作者单位

    Innovative Institute of Electromagnetic Information and Electronic Integration, College of Information and Electronic Engineering, Zhejiang University, Hangzhou, China;

    MaxLinear Inc., Carlsbad, CA, USA;

    Innovative Institute of Electromagnetic Information and Electronic Integration, College of Information and Electronic Engineering, Zhejiang University, Hangzhou, China;

    Innovative Institute of Electromagnetic Information and Electronic Integration, College of Information and Electronic Engineering, Zhejiang University, Hangzhou, China;

    Innovative Institute of Electromagnetic Information and Electronic Integration, College of Information and Electronic Engineering, Zhejiang University, Hangzhou, China;

    Innovative Institute of Electromagnetic Information and Electronic Integration, College of Information and Electronic Engineering, Zhejiang University, Hangzhou, China;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Capacitance; Crystals; Logic gates; Silicon; Delays; MOSFET;

    机译:电容;晶体;逻辑门;硅;延迟;MOSFET;

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