Dynamic data retention and implied design criteria for floating-body SOI DRAM

摘要

A physical MOSFET model in SOISPICE is used to characterize dynamic data retention in PD/SOI DRAM cells. Simulations show that transient parasitic BJT current underlies peculiar data retention, and they suggest how periodic body discharge effected by data refresh with a high flatband-voltage cell transistor can render PD/SOI technology viable and attractive for gigabit DRAM applications.