An 11-bit successive approximation analog-to-digital converter based on a combined capacitor-resistor network

摘要

Within this work an 11-bit integrated Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) based on a combined capacitor and resistor network is presented. Utilizing this approach, the chip area is reduced by the factor of 24 compared to conventional solutions without any interpolation and it occupies only 0.3 mm2. Furthermore, the equivalent capacitance is decreased by connecting two capacitors in series, whereby the matching and the power consumption are improved. The measured Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are below 0.3 and 0.5 LSBs, respectively. The calculated Effective Number Of Bits (ENOB) accounts to 10.72 bits. The chip is produced in 0.6 µm CMOS technology.