Historically, designers have used a hierarchical approach to chip design-breaking the chip into pieces, or blocks-to extend the capacity of design-automation tools. Adopting a hierarchical approach has the advantage of enabling concurrent RTL (register-transfer-level) and physical design, because physical design can start before the netlist is complete. It also allows the use of multiple power regions on a chip. In addition, hierarchical design helps to contain last-minute design changes to local blocks (see sidebar "Glossary of terms"). However, it comes at the cost of much higher project complexity (multiple place-and-route jobs) and loss of optimal results (larger area and lower timing performance). Despite these drawbacks, designers of complex chips, such as graphics processors and microprocessors, have developed methods that exploit the advantages and minimize the drawbacks of hierarchical design by adopting procedures and a design-tool suite that can successfully reassemble the blocks and complete the design for a complex SOC (system on chip).
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