This paper mainly focuses on power efficient and low skew clock network design for three-dimensional ICs based on through- silicon via (TSV). Clock tree synthesis is carried out in two major steps; 1) 3D Abstract clock tree generation; 2) buffering with skew and slew consideration. Firstly we design abstract clock tree by using(3D-MMM) followed by skew and slew aware buffer insertion. We analyze how the inclusion of TSVs will affect RC parasitic of an otherwise 2D clock network design by studying Elmore Delay model for 3D topology. We propose extension to the Exact Zero Skew (EEZE- Extended Exact Zero Skew) algo- rithm by Dr. Tsay for 3D topology which considers TSV resistance-capacitance. This algorithm designs the clock tree by using optimum number of TSVs suitable for the circuit. This is accomplished by merging cost comparison between sets obtained after 3D MMM implementation. This showed 19% to 23% reduction in wire-length. Spice analysis of the obtained clock network resulted in 16% to 18% reduction in clock power dissipation. This indicates that, 1) With optimum TSV count, wire-length of the clock tree reduces by the considerable amount, 2) Small trade-off between optimal TSV count and wire-length, reduces power dissipation.
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