The authors present a high-level simulator that supports a top-down architectural analysis of embedded, custom applications. This tool characterizes more than 50 instruction-set variants and allows data such as instruction cached performance, data cache performance, register set size, and register allocation policy to be evaluated for all the architectures simultaneously. Designers also have more flexibility because they can trade off among high-level design constructs. Thus, they can evaluate relative performance before having to complete the machine specification at a lower level.
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