Hardware IP Protection During Evaluation Using Embedded Sequential Trojan

Narasimhan S.; Chakraborty R. S.; Chakraborty S.

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Hardware IP Protection During Evaluation Using Embedded Sequential Trojan

机译：使用嵌入式顺序木马进行评估期间的硬件IP保护

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来源
《Design & Test of Computers, IEEE》 |2012年第3期|p.70-79|共10页
作者
Narasimhan S.; Chakraborty R. S.; Chakraborty S.;
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作者单位

Case Western Reserve University ,;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Hardware IP Protection; Hardware Trojan; IP Evaluation; IP Piracy;

机译：硬件IP保护;硬件木马;IP评估;IP盗版;

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1. Exposing Hardware Trojans in Embedded Platforms via Short-Term Aging [J] . Surabhi Virinchi Roy, Krishnamurthy Prashanth, Amrouch Hussam, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2020,第11期

机译：通过短期老化在嵌入式平台中曝光硬件特洛伊木马
2. Hardware Trojans Inspired IP Watermarks [J] . Shayan Mohammed, Basu Kanad, Karri Ramesh Design & Test of Computers, IEEE . 2019,第6期

机译：硬件木马启发的IP水印
3. An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification [J] . Maxime Lecomte, Jacques Fournier, Philippe Maurine Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2017,第12期

机译：一种检测硬件木马并协助伪造识别的片上技术
4. On the Detectability of Hardware Trojans Embedded in Parallel Multipliers [C] . Akira Ito, Rei Ueno, Naofumi Homma, IEEE International Symposium on Multiple-Valued Logic . 2018

机译：并行乘法器中嵌入的硬件木马的可检测性
5. Detecting delay anomalies introduced by hardware trojans using chip averaging and an on-chip high resolution embedded test structure. [D] . Ismari, Dylan. 2016

机译：使用芯片平均和片上高分辨率嵌入式测试结构来检测硬件木马引入的延迟异常。
6. Hardware Trojans in Chips: A Survey for Detection and Prevention [O] . Chen Dong, Yi Xu, Ximeng Liu, 2020

机译：筹码中的硬件特洛伊木马：检测和预防调查
7. Hardware Trojans and Other Threats against Embedded Systems [O] . Christof Paar 2017

机译：硬件特洛伊木马和其他针对嵌入式系统的威胁

Hardware IP Protection During Evaluation Using Embedded Sequential Trojan

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