New HDL code generation capabilities simplify programming for ASICs and FPGAs

摘要

Math Works has announced HDL Coder, which automatically generates HDL code from Matlab, allowing engineers to implement FPGA (field-programmable gate array) and ASIC (application-specific integrated circuit) designs from that language.Math Works also announced HDL Verifier, which includes FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs. With these two products, Math Works now provides HDL code generation and verification across Matlab and Simulink. HDL Coder generates portable, synthesizable VHDL and Verilog code from Matlab functions and Simulink models that can be used for FPGA programming or ASIC prototyping and design. Traceability between Simulink models and generated HDL code also supports the development of high-integrity applications that adhere to DO-254 and other standards.