...
首页> 外文期刊>Computing and informatics >A SIMPLE PLL-BASED TRUE RANDOM NUMBER GENERATOR FOR EMBEDDED DIGITAL SYSTEMS
【24h】

A SIMPLE PLL-BASED TRUE RANDOM NUMBER GENERATOR FOR EMBEDDED DIGITAL SYSTEMS

机译:嵌入式数字系统的基于PLL的真随机数生成器

获取原文
获取原文并翻译 | 示例
           

摘要

The paper presents a simple True Random Number Generator (TRNG) which can be embedded in digital Application Specific Integrated Circuits (ASICs) and Field Programmable Logic Devices (FPLDs). As a source of randomness, it uses on-chip noise generated in the internal analog Phase-Locked Loop (PLL) circuitry. In contrast to traditionally used free-running oscillators, it uses a novel method of randomness extraction based on two rationally related synthesized clock signals. The generator has been developed for embedded cryptographic applications, where it significantly increases the system security, but it can be used in a wide range of other applications. The functionality of the proposed solution is demonstrated for the Altera Apex FPLD family, but the same principle can be used for all recent ASICs or FPLDs that include an on-chip reconfigurable analog PLL. The quality of the TRNG output is confirmed by applying special DIEHARD and NIST statistical tests, which pass even for high output bit-rates of several hundreds of Kbits/s.
机译:本文提出了一种简单的真随机数发生器(TRNG),可以将其嵌入数字专用集成电路(ASIC)和现场可编程逻辑器件(FPLD)中。作为随机性的来源,它使用内部模拟锁相环(PLL)电路中产生的片上噪声。与传统使用的自由运行振荡器不同,它使用了一种基于两个合理相关的合成时钟信号的新型随机性提取方法。该生成器是为嵌入式密码应用开发的,它可以显着提高系统安全性,但可以在其他广泛的应用中使用。提出的解决方案的功能已针对Altera Apex FPLD系列进行了演示,但相同的原理也可用于所有最新的ASIC或FPLD,包括片上可重配置模拟PLL。通过使用特殊的DIEHARD和NIST统计测试,可以确认TRNG输出的质量,这些测试甚至对于数百Kbit / s的高输出比特率也可以通过。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号