A MULTICOMPUTER ARCHITECTURE WITH A SEGMENTED SHARED BUS

摘要

Single-bus multicomputer systems can support only a relatively small number of processing elements as the bus quickly becomes the communication bottleneck. Multiple-bus systems provide increased communication bandwidth and can support larger numbers of processing elements. The segmented-bus architecture is an important extension of these systems and offers even more communication bandwidth. The segmented bus contains switches between every pair of adjacent processing elements and can be dynamically segmented into smaller buses that can simultaneously connect more than one pair of processing elements. This paper examines the design of the processing elements, the mathematical modeling and the simulation of the architecture. It relates the performance of the system to the number of processing elements and the bus segmentation and allocation procedure, given a specific load.