A methodology for speeding up loop kernels by exploiting the software information and the memory architecture

摘要

It is well-known that today's compilers and state of the art libraries have three major drawbacks. First, the compiler sub-problems are optimized separately; this is not efficient because the separate sub-problems optimization gives a different schedule for each sub-problem and these schedules cannot coexist as the refining of one, causes the degradation of another. Second, they take into account only part of the specific algorithm's information. Third, they take into account only a few hardware architecture parameters. These approaches cannot give an optimal solution.